Bipolar analog to digital converter



1970 s. e. GORBATENKO ETAL 3,493,958

BIPOLAR ANALOG TO DIGITAL CONVERTER File-d Oct. 7, 1965 v 14Sheets-Sheet 1 ADDER NETWORK gm AND GATES 9 O INVENTORS GEORGE G.GORBATENKO MILTON J.K|MMEL BY ATTORNEY Feb. 3, 1970 s. e. GORBATENKOETAL 3,493,953

BIPOLAR ANALOG TO DIGITAL CONVERTER Filed Oct. 7. 1965 14 Sheets-Sheet 5Feb. 3,1970 sfs. GORBAI'ENKO ETAL 3,493,958

BIPOLAR ANALOG To DIGITAL CONVERTER l4 Sheets-Sheet 4 Filed Oct. 7, 1965T0 AMP LIFIER I8 2 3, 1970 GLGORBATENKO ETAL 3,493,958

- BIPOLAR ANALOG T0 DIGITAL CONVERTER l4 Sheets-Sheet 5 Filed Oct. 7,1965 TO DAC 20l F 1970 a. s. eons/name ET AL 3,493,958

BIPOLAR ANALOG TO DIGITAL CONVERT ER 14 Sheets-Sheet 6 Filed Oct. 7,1965 3, 1970 G. 3. GORBATEQKO ETAL 3,493,958

BIPOLAR ANALOG TO DIGITAL CONVERTER l4 Sheets-Sheet 7 Filed Oct. 7, 19651mm! .1... I i-i$. .mliiwm I B Feb. 3, I970 G. GORBATENKO ET AL BIPOLAANALOG TO DIGITAL CONVERTER l4 Sheets-Sheet 8 Filed Oct. 7. 1965 i--1}--- -1}--- -IL. imel {2. 8m 0 m 8m 0 8m 30 lllll ll- Feb. 3, 1970 G,-egoaaneu-xo T 3,493,958

' BIPOLAR ANALOG TO DIGITAL CONVERTER 14 Sheets-Sheet 9 Filed Oct. 7,1965 m 7 W P l 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I 0 0 0 0 C m M 0 0 0 0 0 0 II I I l I l I 0 0 0 0 I W I I I 0 0 0 I 0 I 0 I 0 I 0 0 l 0 l 0 0 .2 l lO 0 I 0 0 0 I .I 0 0 0 l 0 I mu 0 m 4 I I I I 0 O I I I I 0 0 0 .0 .0 II 0 0 0 O mom I I I l I I 0 0 0 0 0 0 0 0 0 l I I I 0 M 0 I I 0 0 I I II I I I l I I I 0 0 m 5w 0 I I I I I I 0 I I I I I I I I I I W 0 0 0 f.m m I I I l 0 0 0 0 0 l I I I I l I I I O 0 e o I I I I O 0 0 0 0 0 I II I I l 0 0 0 T. d I I I 0 0 O 0 0 0 0 0 I l I I I 0 0 0 0 T U C m I I 0.0 0 0 0 0 0 0 0 0 I l l I 0 0 0 0 N m I I 0 0. 0 0 0 0 0 0 0 0 0 I I l0 0 0 0 0 o I 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I 0 0 0 0 a V V V V V V V V VV V V V V V V W W M n u .7 .5 .4 .2 .0 .0 J j J in :I "W Th .W :W W .n vI R L N R LSL mm 5 MW" 3 WRH S U A 8 TI E o H E E0 I. EmT L ||00 00 000| 0 0| 00 0 00 00 00 00 l 0000 000 ll 0 0 000 0000 OOQO l I I l ll00000000 0|I||l|| 0000000 llllllll 0000000 000000- u 00000000 000000000000000 s. e. GORBATENKO ETAL BIPOLAR ANALOG T0 DIGITAL CONVERTER INPUTST0 80l-80Ic (SIGN) 00000000 00000000 00000000 I l l l I l I l I I I l ll00000000 I I l l I l I l l I l l.| 00000000 00000000 0 0 0 0 0 0 0 0 I 00 0 0 0 0 0 0 0 0 0 0 |IO0 00 00 00 I 00 00 00 00 00 00 0000 0000 Ill0000 O000 Ill 00 0 l l l l I ll 00000000 IIIIIIIIU 00000000 lllll F Feb.3, 1970 Filed Oct. 7, 1965 FlG.llb

Feb. 3, 1910 a @RBATEN O ET AL 3,493,958

BIPOLAR ANALOG TO DIGITAL CONVERTER Filed 001:. 7, 1965 Y 1'4Sheets-Sheet l2 INPUTS TO 80I- 80M OUTPUTS M Z 5 T P c s OVFL SIGN 5(SIGN) G o x o o l o o o o o o 0 o o o o o o l I l o o o 0 H 0 1 I o o oK o o o o o c. a. GORBATENKO if M 3,493,958

BIPOLAR ANALOG 'I'O DIGITAL CONVERTER Feb. 3, 1970 Filed Oct. '2, 1965l4 Sheets-Sheet 125 lnllllllllllllllllllll-llllllll FIGJZO Feb. 3, 1970e. a. CEORBATENKO ETAL v BIPOLAR ANALOG TO DIGITAL CONVERTER 14Sheets-Sheet 14 Filed Oct. 7, 1965 INPUTS |0 0 0 0 0 0 0 O O O O 0 00 0.2 00 00 0 00 0 0 0 00 0 0 0 4 0000 000 0 0 000 0 0 0 8 00000000 00000 00 0 000000 0 O OO 0 00000000 00000 00 00 000000 0 00 0 8.00000 00 0000000 l l I l l l ll 00 0 0 0 00000000 l I I l l I ll 00 000000 0 0 0 0 P00000000 00000 00 00 000000 0 00 M 0 0000000 00000 00 00 000000 0 00 .0O O 0 0 0 0 0 0 0 0 0 00 2 0 0 l00 00 0 ll 00 00 0 00 4 0000 0000 ll 0000 0 00 A B C D E United States Patent M 3,493,958 BIPOLAR ANALOG TODIGITAL CONVERTER George G. Gorbatenko and Milton J. Kimmel, Rochester,Minn., assignors to International Business Machines Corporation, Armonk,N.Y., a corporation of New York Filed Oct. 7, 1965, Ser. No. 493,798Int. Cl. H041 3/00; G06f /02 US. Cl. 340-347 11 Claims ABSTRACT OF THEDISCLOSURE The disclosed successive-approximation analog to digitalconverter has a comparator which provides bipolar signal-level detectionin determining the most significant output digit. The comparator outputis encoded as the true value of the first conversion digit when theanalogsignal polarity is positive and as the complementary value of thedigit when the analog-signal polarity is negative. An analogrepresentation of the encoded value is subtracted from the analogsignal, resulting in a positive difference signal regardless of theanalog-signal polarity. The remainder of the conversion then takes placein the same manner for both positive and negative analog signals. Anerror-correcting feature becomes operative automatically when anincorrect digit conversion presents an out-of-range signal to thecomparator.

The present invention relates to bipolar successive approximation analogto digital converters and, more particularly, to such a converterincorporating means operative during a conversion cycle to correctconversion errors, including errors in sign, occurring during the samecycle.

The so-called successive approximation technique of analog to digitalconversion is a well-known method for producing accurate and, whenimplemented through electronic means, relatively high speed digitalconversions. Prior art electronic converters operating on this principlecompare the unknown analog voltage to be digitized with one or aplurality of precisely known reference voltages in a series of digitgenerating comparison steps. In each step the relative magnitudes of theanalog input or some fraction thereof and the reference voltage arecompared; and, based on this comparison an error or difference voltageis generated which is compared with another reference voltage during thesucceeding step. Each comparison step yields a digit of the final outputand the digits are produced in descending digital order until the thedesired level of quantization is reached.

To enable an analog to digital converter operating on this technique tohandle bipolar inputs, several schemes are known to the prior art. Onevery straightforward bipolar scheme calls simply for the use of twoseparate converters, one set up to handle positive inputs and the otherto handle negative inputs. A polarity detection circuit at the commoninput to the two converters determines the sign of the input voltage andoperates appropriate gating circuits to cause the input signal to bechanneled to the proper converter. It is apparent that this scheme iscostly since it requires two complete converters to obtain but a singleconversion and is subject to erroneous operation to the extent thatthere is no way to correct for an initial wrong decision made by thepolarity detection circuit. Further, this scheme detracts from the speedof the conversion in that some initial period of time is required tomake the polarity decision before the digit generation circuitry canbegin to operate.

Another scheme involves the use of a single, unipolar analog to digitalconverter equipped with means at its input for detectin the polarity ofthe analog signal and Patented Feb. 3, 1970 for inverting the polarityof the signal so that inputs to the converter are always of the samepolarity. The advantage of this scheme over that mentioned above is inthe hardware reduction resulting from the use of only a single convertercircuit. The same speed and reliability drawbacks pertain, however. Inaddition, there is the further drawback that the analog input signal islikely to be degraded in undergoing the initial polarity inversion.

A third bipolar scheme operates upon the philosophy of theabove-mentioned first scheme but achieves somewhat the same hardwaresaving of the scheme just mentioned in that it employs a single analogto digital converter having the necessary extra circuits to enable it tooperate on both positive and negative input signals. Again, an initialpolarity detection circuit is necessary in order to switch the converterto the proper mode of operation and, as before, this initial polaritydecision step detracts from overall conversion speed. Further, no meansare provided in this scheme for correcting the effects of an initialerroneous polarity decision.

It is therefore an object of the present invention to provide animproved bipolar successive approximation type analog to digitalconverter which eliminates the aforementioned drawbacks of the priorart.

It is a further object to extend the principle of the error correctingunipolar analog to digital converter disclosed in co-pending patentapplication Ser. No. 474,255, filed July 23, 1965, to provide a bipolarconverter possessing all the features and advantages appertainingthereto and further having the capability of correcting the effects ofan initial wrong decision made by the polarity determining circuits.

Another object is to provide a bipolar analog to digital converter ofthe successive approximation type which determines the polarity of theinput analog signal coincidentally with a determination of the firstoutput digit, thereby eliminating the need for a separate polaritydetermination time interval.

Still another object is to provide a bipolar analog to digital converterof the successive approximation type which, except for the circuitswhich determine the first output digit, is constructed and operatesidentically to a unipolar converter.

Still a further object is to provide an improved bipolar analog todigital converter of the successive approximation type which inherentlyproduces a digital output which is directly usable in a data processingsystem employing the digital complement form of sign notation.

In accordance with the invention a comparator circuit which providesbipolar signal level detection during the interval in which the first(most significant) output digit is determined produces indications ofboth the sign and the magnitude of the first output digit during thefirst comparison operation. Further, the output of the comparisoncircuit is employed in such a manner as to cause the difference signalgenerated after determination of the first digit to assume the samepolarity (assuming a correct first comparison) regardless of thepolarity of the analog input signal. This is done by utilizing theoutput of the comparator circuit to derive an indication of the truefirst conversion digit when the polarity of the input signal is detectedto be positive and utilizing the comparator output to derive anindication of a digit which is complementary to the true firstconversion digit when a negative input is detected. Subtraction from theinput signal, of an analog level proportional to the first digitrepresentation in the case of a positive input signal and proportionalto the complement of the first digit representation in the case of anegative input signal always results in a positive difference signalthereby permitting the remainder of the conversion to take place in thesame manner for 'both positive and negative inputs. Furthermore, thedigital output generated in the case of a negative input isautomatically the complement of the true output.

Error correction in the converter of the invention operates upon theprinciple that an incorrect comparison decision which generateserroneous sign and digit representations during the first digitgeneration period results in the production of a difference signalhaving a magnitude which is outside the range of voltages normallypresented for comparison during the second digit generation step. Takinginto consideration the known tolerance level of the circuit andcalculating the maximum error of which the circuit is capable in theworst case, the occurrence of such an out of range signal is anindication not only of the fact that an incorrect decision occurred butis an indication of the magnitude of the error as well. Consequently, inthe circuit of the invention means are provided for detecting such outof range signals and for utilizing information thus obtained to correctthe erroneous sign and digit representations. Furthermore, means areprovided for handling such out of range signals just as though they werenormal difference signals resulting from a correct comparison decision.This eliminates any necessity for retracing the conversion process afteran error has been detected and corrected. Still further means areprovided for performing such correction operations substantially at theinstant they occur, therefore permitting execution of a conversion insubstantially the same amount of time as would be required for a circuitnot embodying the novel sign and digit correction feature of theinvention.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of a. preferred embodiment of the invention as illustratedin the accompanying drawings.

In the drawings:

FIG. 1 is a schematic diagram showing the overall conversion circuit ofthe invention.

FIG. 2 is a schematic diagram of the timing circuit 100.

FIG. 3 is a timing diagram illustrating the time relationship betweenthe various output pulses produced by the timing circuit of FIG. 2.

FIG. 4a is a circuit diagram showing the circuit details of the firstdigit generation stage input switch 151 and bipolar digital to analogconverter 201.

FIG. 4b is a circuit diagram showing the circuit details of the seconddigit generation stage unipolar digital to analog converter 202.

FIG. 5 is a circuit diagram of radix amplifier 181.

FIG. 6 is a schematic diagram of the positive comparator bank 300.

FIG. 7 is a schematic diagram of the negative comparator bank 400'.

FIG. 8a is a schematic diagram of the comparator mix circuit 500, thecomparator register 600 and the encode circuit 700.

FIG. 8b is a truth table showing all possible combinations of inputs toencode circuit 700 and the outputs produced in response thereto.

FIG. 9 is a schematic diagram of the first stage DAC register 251.

FIG. 10 is a schematic diagram showing the general arrangement of theadder network 800 and its relationship with the output AND gates 900.

FIG. 11a is a circuit diagram of the adder circuit 801, sign generationcircuit 801a and the AND gates 900 associated therewith shown in FIG.10.

FIG. 11b is a truth table showing four groups of possible combinationsof inputs to the circuits 801 and 801a and the outputs produced inresponse thereto.

FIG. 110 is a truth table showing the remaining possible combinations ofinputs to circuits 801 and 801a and the outputs produced in responsethereto.

4 FIG. 12a is a circuit diagram of the adder circuit 802 and the ANDgates 900 associated therewith shown in FIG. 10.

FIG. 12b is a truth table showing all possible combination of inputs toadder 802 and the outputs produced in response thereto.

Overall circuit With reference to FIG. 1, the overall circuit of theinvention is hereinafter described. The embodiment hereinafter describedperforms digital conversions in the octal system. The octal systememploys the eight digits I I, 2 8, 4, 5, 5 and 7 (the horizontal barsare used to avoid confusion with the similar digit symbols used indecimal notation) and has a radix of I6 (decimal 8). For the sake ofconsistency and to avoid the cumbersome process of transforming valuesfrom octal to decimal and vice versa, all numerical quantities relatingto circuit parameters are hereinafter expressed in octal notation. It isbelieved to be fully within the capabilities of one skilled in theanalog conversion art to employ the principles hereinafter taught inperforming conversions in the decimal or any other number system.

Analog input terminal 10 is connected to an analog voltage source suchas, for example, a sample and hold amplifier which is fed by atime-varying voltage signal to be digitized. A steady-state inputvoltage is transmitted to the first digit generation stage of the analogto digital converter (ADC) via input line 12. This voltage is applied inparallel to the input terminal of a first analog switch 151 and to afirst input port of a non-inverting, subtracting amplifier 1 81 having again of T6. The output line 34 of amplifier 181 is connected to thefirst input port of a second stage subtracting amplifier 182 also havinga gain of 16. Likewise, the output "line 38 from amplifier 182 isconnected to the first input port of third stage times 16 subtractingamplifier 183, and the output line 42 of amplifier 183 is connected tothe first input port of fourth stage times 1 0 subtracting amplifier 184having an output line 46. Second, third, fourth and fifth digit stageanalog switches 152, 153, 154 and 155, respectively, have their inputterminals connected to amplifier output lines 34, 38, 42 and 46,respectively. The output terminals of the five analog switches areconnected to a common signal line 14 which is the input for a bank ofpositive comparator circuits 300 and via the additional line 14a, for abank of negative comparator circuits 400. The input switches arecontrolled by timing pulses issuing on bus 48 from a timing circuit 100.

The comparator circuit 300 comprises nine threshold circuits(differential amplifiers) each having a different voltage referencelevel. For simplicity of description, it is herein assumed that theinput range of the ADC circuit is 56 volts, i.e., the analog inputsignal at terminal 10 never exceeds +TW volts and never falls below ?.77 77 volts. The nine threshold circuits in the bank 300 are referencedto the respective voltage levels of 5 volts, I volt, 5 volts, 8 volts, 4volts, '5' volts, F3 volts, 7 volts and E volts. Negative comparatorbank 400 comprises seven threshold circuits referenced to the respective voltage levels of I volt, volts, volts, -Z volts, 5 volts, 5volts and '7' volts. It is, of course, understood that any desiredbipolar voltage range and corresponding threshold levels may inactuality be employed. As will be hereinafter explained in detail, allthreshold circuits of the circuit 300 which are referenced to a voltagelevel substantially equal to or below the level of the signal on inputline 14 produce a positive level output signal. Those threshold circuitsreferenced to a voltage level higher than that on input line 14 produceno output signal. All threshold circuits of the circuit 400 which arereferenced to a voltage level more positive (algebraically) than thelevel of the signal on input line 14a produce a positive level outputsignal while those negative threshold circuits referenced to a voltagelevel substantially equal to or more negative than that on input line14a produce no output signal.

Threshold circuit output signals issuing from com parator banks 300 and400 in response to an analog signal on lines 14 and 14a are fed viaoutput lines 13 and 15 to a comparator mix circuit 500 where outputsfrom the two comparator banks which are mutually exclusive are channeledthrough OR circuits onto a single one of the output lines 16. Thesignals on the nine lines 16 are entered into a comparator register 600where they are temporarily stored. The digital signals so stored appearon the nine output lines 18 of the register 600 as 1 or 0 voltage levelsand are applied to an encoding circuit 700.

Circuit 700 converts the signal pattern appearing on the lines 18 to asingle BCO digit representing, in the case of a positive input on thelines 14 and 1411, the mag. nitude of the voltage reference level towhich the actuated positive threshold circuit having the highestreference level is tied. In the case of a negative input occurring onlines 14 and 14a during the first digit generation period, circuit 700converts the signal pattern appearing on the lines 18 to a single BCOdigit which is the sevens complement of the true first conversion digitand in addition produces a l-level M bit indicating the negativepolarity of the input signal. Further, during the first digit generationperiod, the circuit 700 is adapted to generate a P bit which is anindication that the input signal exceeds the maximum positive range ofthe converter. T' ning digit generation periods subsequent to the first,the circuit 700 operates on a unipolar basis and the M and P bitsgenerated thereby represent correction information employed, in accordwith the principles of the aforementioned copending patent applicationSer. No. 474,255, filed July 23, 1965, to correct the digital outputresulting from an erroneous comparison having occurred during the firstdigit generation period. The same M and P bits are utilized in accordwith the present invention to correct the erroneous sign indicationwhich may also result from an initial incorrect comparison.

The output from encode circuit 700 consists of three hits of ECGinformation plus the M and P bits appearing on the five output lines20'. The numerical significance attached to the BCO signals on the Z, 2and I lines 20 is Z, 2 and T in accordance with binary convention. Theoutputs on the M and P lines are mutually exlusive.

The signals on the five-wire bus 20 are transmitted to four DAC storageregisters 251, 252, 253 and 254. Each of these storage registersincludes a five-position binary storage circuit. Also included in eachregister are means for selectively gating the signals on the bus 20 intoselected ones of the registers in response to timing signals applied bycircuit 100 via bus 23. ECG and signoverfiow information stored in theregister 251 and ECG and correction information stored in the registers252, 253 and 254 are transmitted via the register output lines 27, 28,29 and 30 both to an adder network 800 and to a plurality of digital toanalog conversion (DAC) circuits 201, 202, 203 and 204, respectively.

As will be subsequently explained in detail, the adder network respondsto the BCO, sign, overflow and correction bits stored in the DACregisters to transfer corrected sign and BCO digit representations tooutput AND gates 900. The DAC circuits cooperate with their associatedsubtracting amplifiers in a manner hereinafter described in detail toproduce a signal at the amplifier out put which is 1 0 times thedifference between the magnitude of the signal fed to the amplifier fromthe preceding stage (or input) and the magnitude of a voltage levelwhich is proportional to the BCO number represented by the digits storedin the DAC register associated with the particular amplifier.

When a BCO digit is stored in any of the DAC registers 252, 253 or 254without a correction bit accompanying it, the voltage level representedto the corresponding amplifiers 182, 183 or 184 by the associated DACcircuit 202, 203 or 204 is directly proportional to the stored BCOdigit. When a correction bit accompanies the BCO digit, the voltagelevel presented to the amplifier is one of two predetermined correctionlevels depending upon whether the correction bit is an M bit ora P bit.

As previously mentioned, encode circuit 700 has a different mode ofoperation during the first digit generation period than in subsequentperiods. This is to take into account the fact that, in order toimplement the heretofore expressed principles of the invention, it isnecessary that the first digit generation comparison be made on abipolar basis. Because of this, DAC circuit 201 is capable of bipolaroperation in a range from +10 volts to -E volts. As previouslymentioned, the M bit generated by circuit 700 during the first digitperiod is a sign rather than a correction bit. Thus, a 0 M bit indicatesthat the polarity of the input signal on lines 14 and 14a was detectedto be positive and a 1 M bit indicates a negative polarity. For positivedigits stored in DAC register 251, DAC circuit 201 operates in exactlythe same manner as DAC circuits 202, 203 and 204, i.e., it represents tothe subtracting amplifier 181 a positive voltage level having amagnitude proportional to the BCD digit stored in the DAC register whenno P correction bit is present and equivalent to a +1 6 volt level whena P correction bit is present. However, when the digit stored in DACregister 251 is negative (accompanied by a l-level M bit) the circuit201 represents to subtracting amplifier 181 a negative voltage levelwhich has a magnitude equivalent to the Es complement of the BCO digitstored in the register 251. The absolute magnitude of the voltage levelrepresented by the circuit 201 in response to a negative input signal istherefore proportional to the complement of the digit stored in register251. That is to say, for the digits of 7, 5, 5, Z, 8, Z T and 0 storedin register 251 along with a l-level M bit DAC circuit 201 is switchedto represent negative analog voltages having values of I volt, 2 volts,volts, 4 volts, 5 volts, 6 volts, -7 volts and T( volts, respectively.The effect of amplifier 181s subtracting these negative levels from theoriginal negative analog input signal is to produce a positivedifference signal on line 34 having a magnitude which is complementaryto the magnitude of the diiference signal which would be generated online 34 by a positive analog input signal of the same magnitude. Theconversion is thereafter completed on a unipolar (positive) basis.

At the end of a five-digit conversion cycle, the corrected sign and BCOsignals appearing at the outputs of adder network 800 are gated todesired utilization circuits through the output AND gates 900 by a pulseissuing on line 25 from circuit 100.

Overall circuit operation assuming a positive input signal and nocomparator error With reference now to FIGS. 1 and 3, a description ishereinafter given of the operation of the circuit of FIG. 1 inperforming a five digit conversion of an analog input signal having amagnitude equal to +0m volt. For the purposes of this portion of thedescription it is assumed that the threshold circuits in the comparatorbanks make correct decisions during each digit generation period.

At the beginning of the cycle, timing pulse supplies a pulse T1 overmulti-wire bus 48 to close the switch 151, transferring the analog inputsignal on line 12 to comparator input line 14. The +0.02T6-v. analogsignal thus presented to the comparator banks 300 and 400 actuates theone threshold circuit in the bank 300 referenced to the volt referencelevel and does not actuate any of the threshold circuits in the bank400. This produces an output signal on one of the nine output lines 16from comparator mix circuit 500. Immediately after switch 151 closes andduring the time that its output is settling to a reasonably steadystate, negative-going pulses A and G are issued from timing circuit .100over multi-wire buses 50 and 23, respectively, to reset the comparatorregister 600 and the DAC registers 251, 252, 253 and 254. Next apositive-going pulse B is issued over bus 50 to gate the signals onoutput lines 16 from the circuit 500 into the comparator register 600.

It is to be noted that the gating pulse B does not appear until near theend of the interval of pulse T1. This allows a maximum amount of timefor the transient effect generated on lines 14 and 14a due to theclosing of switch 151 to settle out. As soon as the comparator registerhas been loaded in response to pulse B and the output signals on thelines 16, encode circuit 700 generates 0 level signals on all outputlines 20, representing the positive BCO digit 0. The sign and BCOsignals thus present on the lines 20 are transmitted to the inputs ofDAC register 251 and a gating pulse C issues over bus 23 to enter theminto the register. The digit and sign indications thus stored inregister 251 represent the magnitude of the most significant digit andthe sign of the output and their presence in the register signifies thecompletion of the first digit generation period.

As soon as digit signals are available on output lines 27 from theregister 251, they are presented to the inputs of DAC circuit 201 viathe multi-wire bus 27a. These digital inputs into the circuit 201precisely alter the voltage presented to the amplifier 181 by DACcircuit 201 such that by superposition an output is produced from theamplifier having a magnitude which is m times the difference between themagnitude of the signal on line 12 (5.075% volt) and the magnitude ofthe voltage level volts) represented by the BCO digit stored in DACregister 251. The magnitude of the signal on line 34 is therefore +02%volt. At substantially the same time the output signals became availableon lines 27 from DAC register 251, timing pulse T1 terminated and pulseT2 was initiated to begin the second digit generation period. Signaltransients caused by the activation of the switches and resistors in DACcircuit 201, by the change in inputs to amplifier 181, by the opening ofswitch 151 and the closing of switch 152 are thus all substantiallysimultaneously initiated and allowed to settle during substantially thesame time period. This conserves circuit time and avoids the situationin which subsequent circuit elements cannot be activated with accuracyuntil prior elements have settled out.

The new signal on comparator input lines 14 and 14a (0% volts) actuatesthe threshold circuit in positive comparator bank 300 referenced to the6 volt level. As during the preceding digit period, none of thethreshold circuits in negative comparator bank 400 are actuated. Again,this produces an output signal on only one of the output lines 16 fromthe circuit 500. During the time in which the new signal on lines 14 and14a was stabilizing and the threshold circuits in the comparator bankswere settling out, a second A pulse issued on timing bus 50 to resetcomparator register 600. A second B pulse then issues on timing bus 50to load the stabilized signals on output lines 16 into the comparatorregister.

Th ensuing presence of a 1 signal on only one of the output lines 18from the register 600 causes encode circuit 700 to again issue zerosignals on all of its output lines 20 to signify the positive BCO digit0. This BCO signal, representing the second most significant outputdigit, is transmitted via the bus 20 to the inputs of DAC register 252whereupon it is caused to be stored therein by a gating pulse B whichissues on bus 23. The presence of this output digit on the output lines28 of register 252 signifies completion of the second digit generationperiod and activates the inputs, via. bus 28a, of DAC circuit 202. Thedigital inputs into DAC 202 precisely alter the voltage presented to theamplifier by DAC 202 such that by superpositon an output is producedfrom the'amplifier having a magnitude which is 10 times the differencebetween the magnitude of the signal on line 34 ((1% volts) and themagnitude of the voltage level (avolts) represented by the BCO digitsstored in register 252. The magnitude of the signal on line 38 istherefore 2% volts. At substantially the same time the output signalsbecame available on lines 28 from DAC register 252, timing pulse T2terminated and pulse T3 was initiated to begin the third digitgeneration period.

As the transients due to activation of the circuits 202, 182, 152 and153 are settling and the line 14 is approaching its new voltage level of2% volts, a third A pulse issues on timing bus 50 to reset comparatorregister 600. The new voltage level on the lines 14 and 14a actuates thethree threshold circuits in positive comparator bank 300 referenced,respectively, to the 0 volt, 1 volt and 2 volt levels and does notactuate any of the threshold circuits in negative comparator bank 400.This combination of comparator outputs causes three of the output lines16 from comparator mix circuit 500 to transmit 1 level signals to theinputs of comparator register 600. T hereupon a third B pulse gates thisnew pattern or threshold output signals into the register 600, settingup output signal on three of the lines 18. Encode circuit 700 respondswith a single output signal on its 2 output line representative of themagnitude ('2') of the third most significant output digit. This signalis gated into DAC register 253 by timing pulse E causing modification ofthe inputs to DAC 203 via the multi-wire bus 29a. An output voltage online 42 of 1.6 volts is obtained from amplifier 183 in the same manneras previously described in connection with amplifiers 181 and 182. Atthis time the timing pulses T3 and T4 terminate and initiate,respectively, to begin the fourth digit generation period.

Thereafter, comparator register 600 is reset by a fourth A pulse and thecomparator input lines 14 and 14a receive, after transients due toactivation of the circuits 203, 183, 153 and 154 have settled, the newvoltage level equal to 1.6 volts. This causes the five thresholdcircuits in positive comparator bank 300 referenced, respectively, tothe 0 volt, T volt, 2 volt, 3 volt and 4 volt levels to transmit 1 leveloutput signals while the outputs of the remaining threshold circuits inbanks 300 and 400 remain at the 0 level. Five of the lines 16 thustransmit signals to the register 600 and, after a fourth B pulse hasgated these signals into the register, encode circuit 700 issues signalson its output lines 20 representative of the digit Z which is the fourthmost significant output digit. This BCO digit is gated into DAC register254 by gating pulse F transmitted from timing circuit via bus 23 causingthe activation of DAC 204 whereby a voltage having a magnitude of 6.5volts is generated on line 46 from amplifier 184 in a manner previouslydescribed in connection with amplifiers 181 and 182.

Thereafter, pulse T4 terminates and T5 is initiated to begin the fifthand final digit generation period. After a fifth A pulse has resetcomparator register 600 and the transients due to the activation of thecircuits 204, 184, 154 and 155 have settled, the new voltage level equalto 6.0 volts appears on lines 14 and 14a. A fifth B pulse then gates thenew signal pattern appearing on lines 16 into the register 600, causingseven of the lines 18 to produce output signals. Encode circuit 700thereafter responds with signals on its 1 and 2 output lines 20representing the final digit 8, which signals are transmitted by lines21 to the adder network 800. Since all comparisons were performedcorrectly by the circuits 300 and 400, the five BCO output digits 0, 0,2, Z and E appearing respectively on the lines 27, 28, 29, 30 and 21 andthe sign bit appearing on M line 27 pass through the adder network 800without change and are presented to the output AND gates 900. Just priorto the occurrence of the initial A and G reset pulses of the ensuingdigit conversion cycle, a pulse H issues from circuit 100 on line 25 toactivate all the AND gates 900, thereby transferring the digital andsign output from the adder network to any desired external utilizationcircuits (not shown). Thereafter, a new analog input voltage ispresented on input terminal 10 and another five-digit conversion isperformed as above described.

Circuit operation assuming a negative input and no comparator errorAssume now that the analog input voltage present on terminal 10 has amagnitude equal to 6.m volts. For the purposes of this portion of thedescription wherein normal operation of the circuit in converting a.negative input voltage is illustrated, it is again assumed that thethreshold circuits in comparator banks 300 and 400 make correctdecisions during each digit generation period.

During the time interval of pulse T1, switch 151 presents the ).m voltanalog input signal to comparator bank; 300 and 400 via the lines 14 and14a. Since the magritude of the signal is between 6 and I volts, nothreshold circuits in either the bank 300 or the bank 400 are actuated.Output lines 18 from comparator register 600 are therefore all at thelevel after the all-zero firing pattern has been gated into the register600 by the first B pulse. In response to this input, encode circuit 700generates 1 level output signals on its 1, 5, T and M output lines 20and a 0 level signal on its P output line. The M signal denotes anegative polarity and the ECG 7 denoted by the signals on the Z, 5, andI output lines is the sevens complement of the true first conversiondigit (5).

This combination of output signals from encode circircuit 700 is gatedinto DAC register 251 by the C pulse and effects through output lines 27and feedback lines 27a, the switching of the inputs to the DAC circuit201 in such a manner to cause that circuit to represent to subtractingamplifier 181 a I volt level. The absolute magnitude (T) of this levelis the 1 0 s complement of the ECG digit (7) stored in the register 251.The output from amplifier 181 appearing on line 34 is an analog signalhaving a magnitude 16 times the difference between the original analoginput signal on line 12 (-fim volts) and the negative level representedby DAC 201. The difference or error signal thus generated by theamplifier 181 has a magnitude of +7.@ volts. It is noted that themagnitude of this signal is the Es complement of the magnitude of thesignal (6.2 16 volts) that would have been generated on line 34 had theoriginal analog input been positive with the same magnitude (seepreceding example).

During the time interval of pulse T2, switch 152 presents the +71% voltanalog signal on line 34 to the comparator banks 300 and 400 to initiatethe second digit generation period. Operation of the comparator circuits300 and the encode circuit during T2 results in generation of a BCO 7 asthe second most significant output digit, which is stored by timingpulse D in DAC register 252. The conversion cycle continues in themanner hereinbefore described for the case of a positive analog inputsignal and third, fourth and fifth output digits representing,respectively, 5, and 5 are generated and stored in DAC registers 253',254 and comparator register 600, respectively. Inasmuch as allcomparison decisions were performed correctly, the output digits aretransferred through adder network 800 unchanged and appear, in responseto output gating pulse H, at the outputs of AND gates 900 as the ECGdigits 77532 accompanied by a minus (1 level) sign bit transferred byoutput line 66 from adder network 800. It is to be noted that thisoutput expressed in BCO, which is the way it actually appears at theoutputs of AND gates 900, is 111 111 101 011 010. This quantity is thebinary twos complement of the quantity 000000010100110 which is a purebinary expression of the magnitude (00246) of the input signal. Theconverter of the invention therefore directly produces binary outputswherein quantities having the same magnitude but opposite sign arerepresnted by numbers which are the binary twos complement of oneanother. This allows the converter to be employed directly in any dataprocessing system which employs this common scheme of sign notation.

Circuit operation assuming an incorrect initial comparator decision Aspreviously stated, the present invention extends the error correctionprinciples of the unipolar analog to digital converter disclosed in theaforementioned co-pending patent application to provide correction oferroneous sign as well as digit indications resulting from an incorrectcomparator decision during the first digit generation period. Theoperation of the circuit of the invention in correcting erroneouscomparator decisions which do not affect the signal of the output is notherein described in detail since such operation is by and large the sameas that described in the aforementioned co-pending patent application.

There are two types of incorrect decisions that a threshold circuit in acomparator bank can make. These two types of misfires are herein termedmalfires and nonfires. The former type of misfire is caused when athreshold circuit fires when it should not have fired and the latter iscaused when a threshold circuit does not fire when it should have fired.To illustrate the occurrence of a malfire, assume that the analog inputsignal is, as in the second illustration above, ).m volts. This is veryclose to being a positive quantity and the threshold circuit incomparator bank 300 which is referenced to a 6 volt potential, inmalfiring because of static inaccuracies in its own circuit,misinterprets this input voltage as being equal to or above 6 volts andproduces an erroneous output signal. The circuit could also malfire ifthe input presented to its was actually equal to or above 6 volts due toerror in the analog switch 151 or in the circuits preceding input line12. Such a comparator malfire sets up an underflow condition in theconverter which initiates a first correction procedure, to besubsequently described in detail, resulting in the subsequent transferof correct sign and output digits in place of the erroneous onesinitially produced as a result of the comparator malfire.

To illustrate a. comparator nonfire, assume that the magnitude of theanalog input signal is +Km volts. The 5 volt threshold circuit incomparator bank 300, in nonfiring because of static inaccuracies in itsown circuit, misinterprets this voltage as being less than 6 volts andthis does not fire. Such a. nonfire could also be caused 'by error inthe digit stage switch 151 or in a circuit preceding it resulting in acomparator input which is actually below 6 volts. When an incorrectdecisions of this type is made, an overflow condition results in theconverter which initiates a second correction procedure.

Referring now to FIG. 1, the two above-mentioned correction proceduresare hereinafter described in terms of specific examples. As mentionedabove in describing a comparator malfire, which initiates the underfiowcorrection procedure, the 6.m 6 volt input signal improperly .causes the5 volt threshold circuit in comparator bank 300 to fire during the firstdigit generation period. The firing pattern thus generated by thecomparator banks and presented to encode circuit 700 on the lines 18makes it appear as though the input signal were between 5 and +1 volt,resulting in the generation of 0 level output signals on all of thelines 20. As mentioned during the preceding discussions, thiscombination of signals denotes to DAC circuit 201 a positive BCO levelof volts. Am plifier 181, in subtracting this level from the actualinput signal and multiplying the difference times 10, generates anoutput signal on line 34 having a magnitude of 0.I2Z( volts. When thisnegative level is presented by switch 152 to the comparator banks duringthe second digit generation period, none of the threshold circuits thereare actuated and no output signal appears on the lines 16. The second Bpulse to comparator register 600 therefore does not gate any 1 levelsignals into the register 600 and the output lines 18 therefrom allremain at the 0 level.

The all-zero input thus transmitted to encode circuit 700 causes theencoding logic therein to set up 0 output signals on the Z, 5, T and Poutput lines 20 and a T signal on the M output line. As brought out inthe preceding discussions, this same combination of input signals intocircuit 700 during the first digit generation period would cause a 11110signal group to appear on the Z, 2, I, M and P output lines 20 denotinga bona fide negative input. However, because all digit stages after thefirst operate on a unipolar basis, this negative level input signalconstitutes an out of range signal which is an indication that anincorrect comparator decision was made during the preceding digitperiod. Timing pulse D gates the 00010 combination of output signalsinto DAC register 252, causing the same signals to appear on outputlines 28. These signals, when fed to DAC 202 via the bus 28a cause thecircuits therein to represent to amplifier 182 a predetermined underflowcorrection level equivalent to -I volt via line 32. This minus levelwhen subtracted from the negative analog input signal on line 34 resultsin an output signal on line 38 having a magnitude equal to .3 2 volts.The magnitude of this signal is exactly the same as it would have beenhad the 5 volt threshold circuit in comparator bank 300 not malfiredduring the first digit generation period. The analog signal has thusbeen corrected and the conversion proceeds through the third, fourth andfifth digit generation periods in exactly the same manner as abovedescribed for the positive input, no-error case.

The BCO 0 which is represented by the Z, 5 and '1' outputs from theregister 252 is, due to the presence of the M correction bit, altered inbeing transferred through the adder network 800 and appears as a BCO '7on output lines 61. Also, the M correction bit causes the BCO 0represented on the I, E and I output lines from DAC register 251 to bechanged by the adder network so that the digital output represented onthe output lines 60 is a BCO 7 Further, the correction bit causes a 1level signal, signifying a minus, to be transmitted on output line 66from the adder network in place of the erroneous plus indicationappearing on the M output line 27 from DAC register 251. The Mcorrection bit generated during the second digit generation periodtherefore causes correction of the sign and magnitude representations ofthe digital output.

To provide an example of the analog and digital correction operationwhich is performed in the event of an overflow condition initiated by acomparator nonfire, it is assumed that the analog input signal on inputline 12 has a magnitude of +1m volt. In this instance an overflowcondition would be caused by nonfiring of the 0 volt threshold circuitin comparator bank 300. In this event none of the comparator thresholdcircuits fire and no 1 level input signals are transmitted to encodecircuit 700 during the first digit generation period. The encode circuitoutput is therefore 11110 as if the actual analog input were less than 0volts but not less than T volt. This output represents a BCO 7 with aminus sign bit. When this combination of signals is presented to theinputs of DAC circuit 201, the ensuing voltage level represented toamplifier 1-81 thereby is T volt, as previously discussed in thenegative input, no error example. The difference or error signalproduced by amplifier 181 in response to this input from circuit 201 hasa magnitude of +10% volts. This signal, appearing on line 34, ispresented to the comparator banks through switch 152 during the seconddigit generation period and actuates all nine of the comparatorthreshold circuits of the positive comparator bank 300 and actuates noneof the negative threshold circuits of the bank 400. This produces outputsignals on all nine of the output lines 16 from comparator mix circuit500, which firing pattern is encoded by circuit 700 to represent thesignal combination of 11101 on output lines 20. This combination ofsignals is stored in DAC register 252 in response to timing pulse D andthereafter appears on output lines 28 to be presented both to DACcircuit 202 and to the adder network 800. The circuit 202, when itreceives the Z, '2, I and P input signals, causes a predeterminedoverflow correction level equivalent to +10 volts to be presented to theamplifier 182 via line 35. The output from amplifier 182 is thus ananalog signal having a magnitude of 2. 16 volts. This is exactly thesame signal level that would have been generated by amplifier 182 hadthe 0 volt threshold circuit in comparator bank 300 fired correctly inthe first instance. In addition, the adder network 800 responds to the Pcorrection bit stored in DAC register 252 to transfer to output ANDgates 900 on lines 61 signals representative of a BCO 0 rather than theRC0 7 represented by the outputs from DAC register 252. Also, thecorrection bit causes adder network 800- to transfer a BCO 0 and a plussign indication to the AND gates 900 via lines 60 and 66 rather than theerroneous BCO 7 and minus sign indications stored in DAC register 251.The remaining three digit generation periods are completed in the mannerpreviously described for the positive input, no-

error case.

In both of the above-described error correction procedures, erroneouscomparison decisions were made during the first digit generation periodas a result of incorrect operation of the 0 threshold circuit in.comparator bank 300. Incorrect decisions may possibly be made by any ofthe threshold circuits in the comparator bank, but inasmuch as erroneousoperation of threshold circuits other than that referenced to the 0 voltpotential do not affect the sign of the digital output, examples of suchoperation are not herein discussed since the principles of suchoperation are fully described in the aforementioned patent applicationdisclosing error correction in a unipolar converter.

As is apparent from the above descriptions, error correction in theconverter of the present invention is based upon the premise that anincorrect comparator decision made during the first digit generationperiod which results in generation of an erroneous sign and firstmagnitude digit causes a difference signal to be generated by the firststage subtracting amplifier which is outside the range of voltage levelswhich could possibly be presented for comparison during the next digitgeneration period under normal error-free operation. That is to say,under normal operations the range of voltages presented to thecomparator banks during the second digit generation period is between 0and +177? volts. The detection of a voltage level which is outside thisrange causes initiation of one of the above generally described errorcorrection procedures.

of FIG. 1 to produce the various waveforms shown in FIG. 3. Anoscillator circuit 101 produces, in a con-

